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STV9410
CRT AND LCD SEMI-GRAPHIC DISPLAY PROCESSOR
. . . . . . . . . . . .
CMOS SINGLE CHIP CRT AND LCD DISPLAY PROCESSOR BUILT IN 6 KBYTE RAM 25 ROWS OR MORE OF 40 CHARACTERS CRT MODE : - ANALOG Y LUMINANCE OUTPUT OF 4BIT DAC - R,G,B DIGITAL COLOR OUTPUTS - FAST BLANKING OUTPUT FOR VIDEO SWITCH COMMAND - SYNCHRONIZATION INPUT AND OUTPUT - MASTER AND SLAVE SYNCHRONIZATION MODES LCD MODE : - 8 GREY LEVELS - 4 BIT DATA WITH CLOCK OUTPUT - 3 OUTPUTS FOR LCD DRIVERS SYNCHRONIZATION - CONTRAST ANALOG COMMAND WITH DAC OUTPUT 128 ALPHANUMERIC CODES AND 128 SEMI-GRAPHIC CODES IN INTERNAL ROM PARALLEL ATTRIBUTES THANKS TO 2 BYTE CODES 128 ALPHANUMERIC AND 96 SEMIGRAPHIC USER DEFINABLE CODES DOWN-LOADABLE IN RAM 3-WIRE ASYNCHRONOUS SERIAL MCU INTERFACE SQUARE WAVE OR LOGICAL PROGRAMMABLE OUTPUT FULLY PROGRAMMABLE WITH 7 16-BIT CONTROL REGISTERS 24-PIN SO OR 20-PIN DIP PACKAGES
Using its 3-wire serial interface, working in both read and write mode to program 7 control registers and to access internal RAM, STV9410 is a highly flexible processor. The STV9410 provides the user an easy to use and cost effective solution to display alphanumeric and semigraphic Informationon CRT and LCD screens.
DIP20 (Plastic Package) ORDER CODE : STV9410P
DESCRIPTION STV9410 controller is a VLSI CMOS Display Processor. Time base generator, display control & refresh logic, interface for transparent MCU memory access, ROM character sets, memory to store display data & page codes and control registers are gathered on a single chip component packed in a short 20 DIP or SO plastic package.
April 1996
SO24 (Plastic Micropackage) ORDER CODE : STV9410D
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STV9410
PIN CONNECTIONS
DIP20
CRT LCD
SO24
CRT RESERVED LCD
XTO XTI
CKO POR
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD SYNC IN
VDD CKD FRAME LOAD
DF
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
-
RESERVED V DD CKD FRAME
LOAD
XTO
XTI
CKO
VDD
SYNC IN VSYNC
C SYNC
-
VSYNC
C SYNC
NCS SDA SCK VREF VSSA VSS
-
POR
I
B
G R
D0
D1
NCS SDA SCK
DF D0 D1
9410-01.EPS - 9410-02.EPS 9410-01.TBL
I
B
G
R
D3 D2
V REF V SSA V SS
RESERVED
D3 D2
V EE
Y
VEE
Y
-
RESERVED
PIN DESCRIPTION
Symbol CRT MODE XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS Y R G B I C SYNC VSYNC SYNC IN VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O I O O I I/O I I S S O O O O O O O O I/O S Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of Y DAC Ref ground of Y DAC Ground Reserved Reserved Luminance output Red output Green output Blue output Fast blanking output Reserved Composite synchro output Vertical synchro output Synchro input +5v power supply Reserved Pin no DIP20 SO24 I/O Description
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STV9410
PIN DESCRIPTION (continued)
Symbol LCD MODE XTO XTI CKO POR NCS SDA SCK VREF VSSA VSS VEE D2 D3 D1 D0 DF LOAD FRAME CKD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 O I O O I I/O I I S S O O O O O O O O I/O S Reserved Crystal oscillator output Crystal oscillator or clock input Clock output Programmable output port Serial interface selection Serial data input/output Serial interface clock input Reset input and ref supply of contrast adjustment Ref ground of contrast adjustment Ground Reserved Reserved Constrast adjustment D2 Data output D3 Data output D1 Data output D0 Data output LCD polarity output Load output (line) Frame output Data Clock +5v power supply Reserved Pin n DIP20
o
SO24
I/O
Description
BLOCK DIAGRAM
XTI
XTO
CKO
VDD
PO R
VREF
S TV9410
CLOCK GENE RATOR
CONTROL P ROCES SING DISPLAY LOGIC S YNC IN
CRT MODE R, G, B C S YNC VSYNC I Y
LCD MODE
D2, D3 , D1
LOAD FRAME D0
TIME BASE
DAC
VEE
DF CKD (SYNC IN)
MCU INTERFACE
6K BYTE RAM
9410-03.EPS
NCS
SDA
SCK
VS S
VS SA
3/25
9410-02.TBL
STV9410
ABSOLUTE MAXIMUM RATINGS
Symbol VDD* VIN* Toper Tstg Ptot Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation Parameter Value -0.3, +7.0 -0.3, +7.0 0, +70 -40, +125 300 Unit V V
o o
C
mW
* with respect to VSS
ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, unless otherwise specified)
Symbol VDD IDD INPUTS NCS, SDA, SCK, SYNC IN, XTI VIL VIH IIL CIN VREF Vrh Vrst RIN VSSA OUTPUTS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR VOL VOH Y Output voltage (VREF=5V, VSSA=0, IOUT=0) LI LD ZOUT Tp Integral linearity Differential linearity Output impedance Propagation time at VOUT 90% of V FINAL, C L=20pF, IOUT=0, VREF=5V, VSSA=0V 0.25 0.1 0.5 80 V V ns
9410-04.TBL
Parameter Supply voltage Supply current *
Min 4.75 -
Typ 5.0 -
Max 5.25 50
Unit V mA
Input low voltage Input high voltage (except XTI) Input leakage current (except XTI) (0 < VIN < VDD) Input capacitance (except XTI) Voltage reference of DAC Reset level on VREF VREF to VSSA internal resistance Reference level of DAC
0 2 -10 1.5 0 0.4 0
10 -
0.8 VDD +10 VDD 0.4 1.0 VDD
V V A pF V V k V
Output low voltage (IOL = 1.6mA) Output high voltage (IOH = - 0.1mA )
0 0.8 VDD
-
0.4 VDD
V V
k
* no load on outputs
4/25
9410-03.TBL
C
STV9410
TIMINGS (VDD = 5V 5%, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz, VIL = 0.8V, VIH = 2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified)
Symbol Parameter Min Typ Max Unit SERIAL INTERFACE NCS, SCK, SDA (Figure 1) Tcsl Tsch Tscl fSCK Tsds Tsdh Tsdv Tsdx Tsdz Tread NCS low to SCK falling edge SCK pulse width high SCK pulse width low Serial Clock Frequency Set up time of SDA on SCK rising edge Hold time of SDA after SCK rising edge Access time in read mode Hold data in read mode Serial interface disable time Delay before Valid Data 2 0 50 20 20 50 0 80 80 4 ns ns ns MHz ns ns ns ns ns s
OSCILLATOR INPUT (XTI) (Figure 1) Twh T wl Fclk RESET (VREF) Tres Reset Low level pulse 2 s Clock high level Clock low level Clock frequency 30 30 8 10 ns ns MHz
OUTPUT SIGNALS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2) Tph,Tpl Tskew Propagation time Skew between R, G, B, I signals
o
CL = 30 pF CL = 100 pF
50 100 30
ns ns ns
(VDD = 5V 5%, VSS = 0V, Ta = 0 to + 70 C, fxtal = 8 to 10MHz, VOL = 0.2VDD, VOH = 0.8VDD, CL = 100pF, unless otherwise specified)
LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3) tCYC tCH tCL tWLD tSU tDH tDF tSUF CKD Shift Clock Period CKD Clock High CKD Clock Low Load Pulse Width Data Set-up Time Data Hold Time DF Delay from Load Frame Set-up before Load 150 4 x Pxtal 150 150 150 150 150 100 ns ns ns ns ns ns ns
9410-05.TBL
ns
5/25
STV9410
Figure 1 : Microcontroller Interface Timings
NCS t csl t sch SCK t sds t scl t sdh A8 A9 A6 WRITE A7 t sdv D0 D1 t sdx D6 READ t sdz D7
9410-04.EPS 9410-06.EPS 9410-05.EPS
t read
SDA
Figure 2 : Output Signals Delay versus Clock
t wh XTI t pl t ph OUTPUT t skew OUTPUT t wl
Figure 3 : LCD Interface Timings
t CH CKD t CYC LOAD t SU D0, D1 D2, D3 t DF DF t SUF t DH t WLD t CL t CLD
FRAME
6/25
STV9410 2. FUNCTIONAL DESCRIPTION
STV9410 display processor operation is controlled by a host microcomputer via a 3-wire serial bus. It is fully programmable through seven internal read/write registers and performs all the display functions either for CRT screen or LCD passive matrix by generating pixels from data stored in its internal memory. In addition, the host microcomputer can have straightforward accesses to the on-chip 6 Kbytes RAM, even during the display operation. The following functions are integrated in the STV9410 : - Crystal oscillator, - Programmable timing generator, - Microcomputer 3-wire serial interface, - ROM character generatorincluding 128 alphanumeric and 128 semigraphic character sets, - 6 Kbytes on chip RAM to store character codes, user definable character sets, and any host microcomputer data, and in CRT mode : - Y output driven by a 4-bit DAC, - Programmable master or slave synchro modes, - R, G, B, I outputs, in LCD mode : - LCD interface for passive multiplexed matrix, - 7 grey levels plus black. 2.1 SERIAL INTERFACE This 3-wire serial interface can be used with any microcomputer. Data transfer is supported by hardware peripherals like SPI or UART and can be emulated with standard I/O port using software routine ( see application note ). NCS input enablestransfer on high to low transition and transfer stays enabled as long as NCS input remains at logical low level. NCS input disables transfer as soon as low to high transition occurs, whatever transfer state is, and transfer remains disabled as long as NCS input remains at logical high level. SCK input receives serial clock; it must be high at the beginning of the transfer; data is sampled on rising edge of SCK. SDA input (in write mode) receives data which must be stable at least tsds before and at least tsdh after SCK rising edge. In read mode, SDA receives address and read command (R/W bit) and then it switches from input state to output state to send data (see Data transfer and Application Note). Data Transfer in Write Mode The host MCU writes data into STV9410 registers or memory. The MCU sends first MSB address with R/W bit clear, it sends secondly LSB address followed by data byte(s). STV9410, then, internally increments received address, ready to store a second data byte if needed, and so on, as long as NCS remains low (see Figure 4). LSB are sent first. Data Transfer in Read Mode The host MCU reads data from STV9410 registers or memory. The MCU sends first MSB address with R/W bit set, it sends secondly LSB address, then SDA pin switches from input state to output state and provides data byte(s) at SCK MCU clock rate. Notice that a minimum delay is needed before sending the first SCK rising edge to sample the first data bit (at least 2s). After each data byte STV9410 internally increments address and it sends next data at SCK frequency. SDA remains in output state as long as NCS remains low (see Figure 5). Address auto-incrementation allows host MCU to use 8, 16, 32-bit data words to optimize transfer rate. LSB are sent first. SCK max speed is 4MHz.
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STV9410
Figure 4 : Serial Interface Write Mode
NCS
SCK
SDA
A8
A9
A10 A11 A12 A13 @ MSB
W
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
@ LSB
Data byte 1
NCS
SCK
SDA D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
9410-07.EPS
data byte n - 1
data byte n
Figure 5 : Serial Interface Read Mode
NCS 2s min. SCK
SDA
A8
A9
A10 A11 A12 A13 @ MSB
R
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
@ LSB INPUT
Data byte 1 OUTPUT
SDA Pin
NCS
SCK
SDA
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
data byte n - 1
data byte n OUTPUT INPUT
9410-08.EPS
SDA Pin
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STV9410
2.2. ADDRESSING SPACE STV9410 registers, RAM and ROM are mapped in a 12 kbytes addressing space. The mapping is the following :
0000 h 6144 RAM bytes 17FF h 1800 h 1FFF h 2000 h 24FF h 2500 h 27FF h 2800 h 2CFF h 2D00 h 2FEF h 2FF0 h 2FFF h Display memory DRCS Descriptor tables User memory
HSYN
2FF5 2FF4 SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
SU (7:0) : Synchro rising edge position SD (7:0) : Synchro falling edge position
POR
2FF7 2FF6 VOE N7 : : : : N6 N5 N4 N3 N2 TE N1 PV N0
Empty Area 1280 slices ROM G0 Empty Area 1280 slices ROM G1 Empty Area Internal Registers
VOE TE PV N (7:0)
Video output enable Timer enable Port value Square wave period
ADDR
2FF9 2FF8 P12 P11 P10 G12 G11 G10 P9 P8 P7 P6
A12 A11 A10
P (12:6) : Address of first descriptor of page to display G (12:10) : User definable graphic character set address A (12:10) : User definable alphanumeric character set address
DISP
2FFB IMG GMG RMG BMG 2FFA FLE CCE IN1 IN2 HIC
BR3 BR2 BR1 BR0
2.2.1 Register Set VERT
2FF1 2FF0 LCD ILC C/H V/P VSE HSE F (8:0) : : : : : : : LCD ILC F7 F6 C/H V/P VSE HSE F5 F4 F3 F2 F1 F8 F0
LCD/CRT mode Interlaced/non-interlaced Composite/horizontal synchro Vertical synchro/real time port Vertical synchro enable Horizontal synchro enable Number of scan line per frame
IMG, GMG, : Margin value of I, G, R, B outputs RMG, BMG HIC : High contrast, forces black and white on outputs FLE : flashing enable CCE : Conceal enable IN1, IN0 : Fast blanking mode BR (3:0) : Luminosity adjustment on Y output
CURS
2FFD 2FFC CEN CBL CUL C (12:1) : : : : CEN CBL CUL C8 C7 C6 C5 C12 C11 C10 C4 C3 C2 C9 C1
HORI
2FF3 2FF2 L5 L4 L3 MG2 MG1 MG0 L2 L1 L0
Cursor Cursor Cursor Cursor
enable blinking underlining address
MG (2:0) : Margin duration L (5:0) : Line duration
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STV9410
2.2.2 Descriptor UNIFORM
MSB LSB RTP FFB I C (2:0) SL (7:0) : : : : : 0 RTP FFB I C2 C1 C0 0000h Descriptor (Table 1) 0040h (for page 0) Descriptor (Table 2) 0080h (for page 0) Page 0 Row 1
2.2.4 Example of RAM Maping
SL7 SL6 SL5 SL4 SL3 SL2 SL1 SL0 Real time port Field flyback Fast blanking Strip color (G, R, B) Number of scan line of the strip
64b 64b 80b 80b
CHARACTER
MSB LSB RTP DE ZY C (12:1) : : : : 1 C8 RTP DE C7 C6 ZY C5 C12 C11 C10 C4 C3 C2 C9 C1 07D8h
0800h 00A8h
Code 0 to 39 Page 0 Row 2 Code 0 to 39
2 Kbyte
Real time port Display enable Vertical zoom Address of first character to display
~ ~
Page 0 Row 24 Code 0 to 39
~ ~
80b 64b 64b 80b 80b
~ ~
Descriptor (Table 1)
2.2.3 Code Format ALPHANUM
MSB (ODD) LSB (EVEN) 0 IV CHARACTER NUMBER DW DH FL FC2 FC1 FC0
(for page 1)
Descriptor (Table 2) (for page 1) Page 1 Row 1 Code 0 to 39 Page 1 Row 2 Code 0 to 39
2 Kbyte
CHARACTER NUMBER : lower than 80h in ROM from 80h to FFh in RAM IV : Inverted video DW : Double width DH : Double height FL : Flashing FC (2:0) : Foreground color (G, R, B)
~ ~
Page 1 Row 24 Code 0 to 39
~ ~
80b 10b 10b
~ ~
1000h Alphanum Character 0 Alphanum Character 1
GRAPHIC
MSB (ODD) LSB (EVEN) 1 CHARACTER NUMBER BC2 BC1 BC0 FL FC2 FC1 FC0
~ ~
Alphanum Character 93 Page 0 Row 0 Code 0 to 39 Free
1400h Graphic Character 0
~ ~
10b 80b 4b 10b 10b
~ ~
1 Kbyte
CHARACTER NUMBER : lower than 80h in ROM from 80h to DFh in RAM BC (2:0) : Background color (G, R, B) FL : Flashing FC (2:0) : Foreground color (G, R, B)
CONTROL
MSB (ODD) LSB (EVEN) EOL IF, IB UL CC BC (2:0) HG FC (2:0) 10/25 : : : : : : : 1 1 1 1 EOL IF IB UL CC
Graphic Character 1
~ ~
Graphic Character 93 Page 1 Row 0 Code 0 to 39 Free
~ ~
10b 80b 4b
~ ~
1 Kbyte
BC2 BC1 BC0 HG FC2 FC1 FC0
End of line Fast blanking foreground/background Underline Conceal Background color (G, R, B) Hold graphic Foreground color (G, R, B)
9410-09.EPS
17FFh
STV9410
2.3 CLOCK AND TIMING GENERATOR The whole timing is derived from XTI input frequency which can be an external generator or a crystal signal thanks to XTO/XTI oscillator.This clock is also pixel frequency which can be chosen between 8MHz to 10MHz (pxlck). This clock is available on CKO pin. It should be use for the MCU, saving a crystal in the application. The active area of a video line is 320 pixels periods long (40 characters of 8 pixels wide). Number of lines per frame, margin width, line duration, leading and trailing edges of horizontal synchronizationare fully programmable in CRT mode using VERT, HORI, HSYN registers. A RESET, can be applied to STV9410 by pulling low VREF pin ( 0.4V). On RESET, default values are forced into configuration registers and video outputs are at low level. All unused bit of registers are always read as "0". Figure 6 : Vert Register Scan Lines Programmation
2FF1 2FF0 Nb of S can Lines LS B HEXA
2.3.1 Time Base Registers Vertical Time Base and Configuration Register (VERT) Internal address : 2FF1-2FF0 h RESET value :01-36 h (@ = RESET default configuration)
2FF1 h LCD ILC @ 0 0 2FF0 h @ LCD ILC C/H V/P VSE HSE F (8:0) F7 0 F6 0 C/H V/P VSE HSE 0 0 0 0 F5 1 F4 1 F3 0 F2 1 0 F1 1 F8 1 F0 0
: 1 LCD mode 0 CRT mode @ : 1 Interlaced scanning 0 non-interlaced scanning @ : 1 CSYNC is composite synchro 0 CSYNC is horizontal synchro @ : 1 VSYNC is vertical synchro 0 VSYNC is RTP bit of current descriptor @ : 1 enable vertical synchro with SYNC IN 0 disable @ : 1 enable horizontal synchro with SYNC IN 0 disable @ : scan line number per frame (@ 312)
LCD ILC
X X
C/H
X
V/P VSE HSE
X X X
-
F8
0 0
F7
0 0
F6
0 0
F5
0 0
F4
0 0
F3
0 0
F2
0 0
F1
0 0
F0
0 1
F(0:8) + 2
Not allowed 3 16 64
01
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 0 0 0 0 0 0 1 1 1
0 0 1 1 1 1 0 0 0 0 0 0 1 1 1
0 1 1 1 1 1 0 0 1 1 1 1 0 1 1
0 1 0 1 0 1 0 0 1 1 1 1 1 1 1
1 1 0 0 1 1 0 0 0 0 0 1 1 1 1
1 1 0 1 1 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 0 0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1
0E 3E 62 76 EE F8
04
100 120 240 250
262 263
05
310 312 313 320 480 512 513
34
36 37 3E DE FE FF
9410-10.EPS
F[8:0] = Scan Line Number - 2
11/25
STV9410
Margin and Horizontal Time Base Register (HORI) Internal address : 2FF3-2FF2 h RESET value :03-3F h (@ = RESET default configuration)
2FF3 @ 2FF2 @ 0 0 0 0 0 L5 1 0 L4 1 0 L3 1 MG2 MG1 MG0 0 1 1 L2 1 L1 1 L0 1
Horizontal Synchronization Register (HSYN) Internal address : 2FF5-2FF4 h RESET value :E6-DC h (@ = RESET default configuration)
2FF5 @ 2FF4 @ SU7 SU6 SU5 SU4 SU3 SU2 SU1 SU0 1 1 1 0 0 1 1 0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 1 1 0 1 0 1 0 0
MG(2:0) : Left and right margin duration (@ = 4s) MarginDuration MG = -1 8 pxlck L(5:0) : Line duration (@= 64s) Line Duration L= -1 8 pxlck
SU(7:0) : SYNC rising edge position (@ = 57.75s) Rise Edge Position SU = -1 2 pxlck SD(7:0) : SYNC falling edge position (@= 53.25s) FallingEdge Position SD = -1 2 pxlck
Figure 7 : HSYN Register Synchro Pulse Programmation
Qz = 8MHz
REG Active area Register Value Duration Duration (s) (nber of char.)
HORI
(L = 3F)
64s 1s 1s 40s 21s 46s 48s
64
FIXED
1
HORI
(MG = 0)
1
FIXED
40
RESULT
21
HSYN
(SU = B7)
46
HSYN
(SD = BF)
48
HSYN PULSE
Positive Pulse
HSYN
(SU = BF)
48s 46s
48
HSYN
(SD = B7)
46
9410-11.EPS
HSYN PULSE
Negative Pulse
12/25
STV9410
Figure 8 : Horizontal Synchronization Timing
DESIGNATION PIXEL CLOCK START Y OUTPUT DAC output START "HORT" MSB REG "HORT" LSB REG "HSYN" LSB REG "HSYN" MSB REG HSYN PULSE 8pxlck Fixed = (MG +1) x 8 x pxlck = (L +1) x 8 x pxlck = (SD + 1) x 2 x pxlck = (SU + 1) x 2 x pxlck
9410-12.EPS
TIMING DIAGRAM
COMMENTS Crystal = 8MHz pxlck = 125ns 0 = origin
0 Start
Margin
Active Area (320 pixels)
Margin
End of line
0
Video Validation and Port Register (PORT) Internal address : 2FF7-2FF6 h RESET value :00-00 h (@ = RESET default configuration)
2FF7 @ 2FF6 @ VOE VOE 0 N7 0 0 N6 0 0 N5 0 0 N4 0 0 N3 0 0 N2 0 TE 0 N1 0 PV 0 N0 0
mode (CRT or LCD), be fulfiled : - SU SD SU + 1 SD + 1 < L and 4
4
TE
PV N(7:0)
: Video Output Enable 1 enable synchro & video outputs 0 disable synchro & video outputs @ (@ Output Y, CSYNC, VSYNC, R, G, B, I, POR, and DF are grounded, Input SYNC IN is high impedance) : Timer Enable 1 POR provides a square wave signal with a period of 16 x N(7:0) x pxlck 0 POR output is PV bit @ : Port Value POR output value if TE=0 (@=0) : Square wave period on POR if TE=1 (@=0)
PFrame PFrame
[ F(8:0) + 2 ] [ L(5:0) + 1 ] x 8 - I n LCD, u sing a 240 line s matrix, an d MG(2:0) = 0, Pxclk =
BEWARE The programmation of VERT, HORI, HSYN registers must be consistent. To get a proper work of the controller, the following conditions must, in any
240 x 43 x 8 Interlaced mode conditions : SU + 1 SD + 1 and (MG + 1) + 42 4 4
13/25
STV9410
2.3.2. CRT Mode In CRT mode, the Vsync signal appears at the first two lines of the first strip of the descriptor list. It is recommended to provide an uniform blanked (with FFB bit) strip as first descriptor. The scan line number of this strip have to be equal or higher than scan line number of the vertical blanking Interval. Master Mode This mode is selected by writing VSE and HSE bit of VERT register with logical value "0". Non-interlaced mode is selected by writing ILC bit of VERT register with logical value "0". Horizontal or composite synchronization signal is output on CSYNC pin, Vertical synchronization signal is output on VSYNC pin. Signal waveforms are described in Figure 9. Interlaced mode is selected by writing ILC bit of VERT register with logical value "1". Even frame is identical to non-interlaced frame. VSYNC PULSE is low during second half of last line of previous Odd frame and during the two first lines of current Even frame. Odd frame is one scan line more than Even frame. VSYNC PULSE is low during the two first lines and up to first half of the third line of current Odd frame. Half line corresponds to 17th character position. Signals waveforms are described in Figure 10. Slave Mode This mode is activated by writing VSE and/or HSE bit of VERT register with logical value "1". Then SYNC IN input signal is sampled according to procedure described below. Vertical Synchronization SYNC IN signal may be either a vertical synchronization or a composite synchronization. It is sampled on first pixel of each scan line active area. As soon as SYNC IN signal low level is detected, vertical time base counter F(8:0) of VERT register is reset without any modification of other time base registers. Horizontal Synchronization SYNC IN is sampled one pxlck before and one pxlck after internal horizontal pulse transition. If falling edge is not found, one pixel period is added to internal line duration. Using a line frequency locked clock applied on XTI, internal scan line becomes phase locked after few scan line periods at programmed value (see Figure 11). 2.3.3 LCD Mode LCD mode only works as a master mode with 320 pixels per line. Internal algorithm allows 8 grey levels on passive LCD matrix. Number of scan line is programmable. In order to get maximum refresh frequency of display, margin and line duration must be reduced to miminum. Interlaced mode and external synchronization are not allowed. The 1st line of the first descriptor in the description list correspond to the first line of the LCD display. Y output provides a programmable voltage usable to adjust contrast of LCD display. To reduce supply current consumption, when Y output is unused, VSSA must not be connectedto ground, and VREF pin works as a reset pin. Notice that SYNC IN Pin provides (CKD) data clock signal. 2.4 POR OUTPUT POR is a standard I/O pin programmable at logical level "1" or "0". It can also provide a programmable square wave signal of period P = 16 x N(7:0) x pxlck (0 N 255). It can drive a capacitive buzzer (see application diagram at page 22). RESET value of PORT is "0".
Figure 9 : ODD and EVEN Synchronization Pulses in Non-interlaced Mode
DESIGNATION H SYNC PULSE C SYNC PULSE VSYNC PULSE "VERT" LSB REG LINE NUMBER
* Internal logic adds one more line
TIMING DIAGRAM
COMMENTS Horizontal Synchro Composite Synchro Vertical Synchro
FN - 1 N
FN N+1
FN
+ 1*
F0 1
F1 2
F2 3
F3 4
Programmed value of F (8 : 0) is N
9410-13.EPS
N +2
Frame number of lines is N + 2
14/25
STV9410
Figure 10 : Interlaced Mode Synchronization Pulses
DESIGNATION H SYNC PULSE TIMING DIAGRAM COMMENTS Horizontal Synchro Composite Synchro Programmed value of F (8 : 0) is N EVEN frame number of lines is N + 2
C SYNC PULSE
"VERT" LSB REG
FN - 1 N
FN
N+1
FN + 1 N +2
F0
1
F1
2
F2
F3
LINE NUMBER
3
Current Picture ODD Frame
4
Previous Picture EVEN Frame
V SYNC PULSE
Vertical Synchro ODD Frame
H SYNC PULSE
Horizontal Synchro
C SYNC PULSE
"VERT" LSB REG
LINE NUMBER
FN
N+ 1
FN + 1
N+2
FN + 2
N +3
F0
1 Current Picture
F1
2
F2
F3
Programmed value of F (8 : 0) is N ODD frame number of lines is N + 3 Picture number of lines is 2N + 5
3
4
ODD Frame V SYNC PULSE
EVEN Frame
Vertical Synchro EVEN Frame
Start ZONE CHAR NUMBER
Margin
Active Area
Margin
End of line Characters Position Horizontal Synchro
1234
15 16 17 18
38 39 40
H SYNC PULSE LINE 3 ODD FRAME
LINE N + 3 ODD FRAME
Composite Synchro
9410-14.EPS
Composite Synchro
15/25
STV9410
Figure 11 : Synchronization on SYNC IN External Signal
VERTICAL SYNCHRONIZATION DESIGNATION TIMING DIAGRAM COMMENTS
PIXEL CLOCK Margin Y OUTPUT H Pulse SYNC IN VERTICAL PULSE F (8 : 0 ) Fx S F0 Active Area H Pulse Margin
Sampling Clock
Sampling on first pixel of active area S = 0 clear F (8 : 0) only
HORIZONTAL SYNCHRONIZATION DESIGNATION TIMING DIAGRAM COMMENTS Sampling Clock
PIXEL CLOCK
INTERNAL H SYNC DURATION = L (5 : 0) EXTERNAL H SYNC UNLOCKED EXTERNAL H SYNC LOCKED
Sampling window for H Synchro L = L+ 1 L= L Line Duration Increase + 1 Good Line Duration
9410-15.EPS
3. INTERNAL REGISTER DESCRIPTION
STV9410 is programmable with 7 registers of 16 bit each. These registers can also be programmed in byte mode. Not significant bit must be cleared in order to be compatible with next generation products. 3.1 TIME BASE REGISTERS Registers VERT, HORI, HSYN and PORT are described in chapter 2.3 3.2 ADDRESS REGISTER ( ADDR ) Internal address : 2FF9-2FF8 h
RESET value :00-00 h (@ = RESET default configuration)
2FF9 h @ 2FF8 h @ 0 0 P12 P11 P10 0 0 0 G12 G11 G10 0 0 0 P9 0 0 P8 0 P7 0 P6 0
A12 A11 A10 0 0 0
P(12:6) : Page first descriptor address, P(5:0)=0 @ G(12:10) : Graphic character set MSB address, G(9:0)=0 @ A(12:10) : Alphanumeric character set MSB address, A(9:0)=0 @
NB : as addresses are in RAM area, address bit 13 is reset to "0"
16/25
STV9410
Figure 12 : ADDR Register and Descriptor List Address
2FF9 ADDR REGISTER P12 P11 P10 P9 P8 P7 P6 2FF8 G12 G11 G10 A12 A11 A10
Used for RAM character sets REAL ADDRESS PROG VALUE REAL ADDRESS PROG VALUE REAL ADDRESS PROG VALUE 0 2 1 5 1 0 1 0 9 0 2 0 1 0 1 7 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 (0800h)
0
0
0 -
0
0
0
(15C0h)
0
0
0 -
0
0
0
(0A40h)
64 bytes blocks
3.3 DISPLAY REGISTER (DISP) Internal address : 2FFB-2FFAh RESET value :00-00 h (@ = RESET default configuration)
2FFB IMG GMG RMG BMG @ 0 0 0 0 2FFA FLE CCE @ 0 0 IMG, GMG, RMG, BMG HIC IN1 0 0 0 0 HIC 0
BR(3:0) : This value is combined with pixel value to drive Y DAC in CRT mode : Y= 4xG + 2xR + B + BR(2:0) + 3x(R or G or B) (logical or) R, G, B, I, Y, = 0 during line flyback.
IN0 BR3 BR2 BR1 BR0 0 0 0 0 0
Black level is output with R, G, B = "0". White level is output with R, G, B = "1". During frame flyback, R, G, B, I, Y provides signal according to uniform strip descriptor FFB bit state (see chapter 4.2.1) During LCD mode BR(3:0) drives continuously Y DAC. Notice that only bit 0 to 2 of BR are used in CRT mode. 3.4. CURSOR REGISTER (CURS) Internal address : 2FFD-2FFC h RESET value : 00-00 h (@= RESET default configuration)
2FFD @ 2FFC @ CEN CBL CEN CBL CUL 0 0 0 C8 0 C7 0 C6 0 0 C5 0 C12 C11 C10 0 0 0 C4 0 C3 0 C2 0 C9 0 C1 0
: M a rg in v a lu e o f I, G , R, B o u tp ut s and background color and insertion default attribute of next alphanumeric character. In case of graphic characters only I is default attribute. : Forces alphanumeric characters background black (R, G, B = 0), and foreground white (R, G, B = 1) for maximum contrast, 0 = disable @ FLE : Flashing enable, 0 = disable @ CCE : Conceal enable, 0 = disable @ IN1,IN0 : Insertion attribute mode selection. Mode selects value of I output during active area of scan line in CRT mode; I output value (during margin) is programmed with DISP register; during uniform strip I output value is set according to strip descriptor. During active time slot : 0 0 : I output gets value of current code I attribute (margin attribute or control character attribute ) @ 0 1 : I is set ("1") 1 0 : I output gets value of current code I attribute if I=0 R,G,B are reset to "0" 0 1 : Reserved mode
: Cursor enable, 0 = disable @ : 0 cursor blinking off, character blinking attribute unchanged @ 1 cursor blinking on, blinking is mixed with character blinking attribute. Blinking frequency is around 1Hz and duty cycle 50% CUL : 0 character underline attribut is complemented on cursor position @ 1 character color is complemented on cursor position C(12:1) : Cursor address (not a screen position) 17/25
9410-16.EPS
STV9410 4. DISPLAY CONTROL
4.1 SCREEN DESCRIPTION A screen is composed of successive scan lines gathered in one or several strips. Each strip is defined by a descriptor stored in memory. A list of descriptors allows screen composition, different screens can be defined in memory (see application note and Figures 13, 14.). Two kinds of strip are available : - Uniform color strip Applications : - vertical front and back porch - vertical synchro - border lines Parameters : - number of scan lines - color - Character strip Characters and attributes are defined by a succession of codes stored in memory; thanks to the character code, a memory address is calculated and used to get the character pattern. Parameters : - address of the first code - size, display enable
Figure 13 : Programmation of Number of Scan Lines - Vertical Register VERT (2FF0/2FF1) and Descriptor List
DESCRIPTOR LIST CONTENTS 1460 U0* 0A02 F8AA 20AB 48AB U1 R0* R1 R2 A8AA D0BA 1402 R18 R19 U2 1906 U3 1903 U4 1907 U5
SCAN LINES SUM
20 20
10 30
10 40
10 50
10 60
10 220
10 230
20 250
25 275
25 300
25 325
VERT REGISTER COMMENTS
242 Scan Lines (00F0h) U2 Strip is cut (red uniform strip)
VERT REGISTER COMMENTS
312 Scan Lines (0136h)
9410-17.EPS 9410-18.EPS
U2 (red), U3 (yellow), U4 (cyan) and part of U5 (white) uniform strip are displayed
* U0 is uniform strip number 0, R0 is character strip number 0
Figure 14 : Relation between Screen Location/Descriptor Pointer/RAM Page Codes
Address of the list OTHER 25th ROW CODES OTHER 1st ROW CODES 3rd ROW CODES 2nd ROW CODES OTHER 23th ROW CODES OTHER RAM PAGE CODES LOCATION ROW 22 ROW 2 ROW 24 UNIF 1 RAM DESCRIPTOR LIST 23th CHARACTER ROW 24th CHARACTER ROW * 25th CHARACTER ROW BOTTOM UNIFORM STRIP UNIF 0 ROW 0 ROW 1 ROW 2 ADDR REGISTER
* Identical to row 2
TOP UNIFORM STRIP 1st CHARACTER ROW 2nd CHARACTER ROW 3rd CHARACTER ROW
SCREEN
18/25
STV9410
4.2. STRIP DESCRIPTOR Each strip is defined by 2 bytes. During the vertical retrace, an internal descriptor address counter is initialised with the value P(12:0) of ADDR register; on the trailing edge of vertical synchro, the first strip descriptor is loaded into the display controller; if it is an uniform strip, selected color is displayed during the corresponding number of scan lines; if it is a character strip, left margin followed by text, followed by right margin are displayed during 10 scan lines ; the next descriptor is then read, and the same process is repeated until the last scan line. This information being given by the vertical timing generator.
FFB : Field Flyback 0 R, G, B, I and Y outputs are defined by corresponding bit of DISP for margin and C(2:0) and I for active area 1 R, G, B, I and Y outputs are cleared during Field Flyback, whatever other parameters are. I : 0 Fast Blanking Disable 1 Fast Blanking Enable C(2:0) : G, R, B, value during the active area of the strip (320 pixels) SL(7:0) : Number of scan lines of the strip, minimal value is 1.
4.2.2. Character Strip
1 C8 RTP RTP C7 DE C6 ZY C5 C12 C4 C11 C3 C10 C2 C9 C1
4.2.1 Uniform Strip
0 SL7 RTP RTP SL6 FFB SL5 SL4 I SL3 C2 SL2 C1 SL1 C0 SL0
: Real Time Port RTP bit value is output on VSYNC when V/P bit of VERT register is "0", along the complete duration of the strip scan line. Not used in LCD mode.
: Real Time Port RTP bit value is output on VSYNC when V/P bit of VERT register "0", along the complete duration of the strip line, during the whole strip. DE : Display Enable 0 display off, the strip is displayed with margin attributes IMG, GMG, RMG, BMG bit of DISP register, 1 display on, the strip works as selected. ZY : Vertical Zoom 0 normal display mode 1 all scan line are doubled, providing a vertical zoom effect C(12:1) : Address of the first code to display
Figure 15 : Character Strip Descriptor - First Character Address Selection
MSB DESCRIPTOR 1 RTP DE ZY C12 C11 C10 C9 C8 C7 C6
LSB C5 C4 C3 C2 C1 C0
EFFECTIVE ADDRESS BINARY ADDRESS BINARY DESCRIP. PROG VALUE 1 0
1 1 A 0 1 1 0 0 A 1 1
5 0 0 1 1 1 1 F 1 1
F 1 1 1 1 0 0 8 0 0
0 0 0 0
EFFECTIVE ADDRESS BINARY ADDRESS BINARY DESCRIP. PROG VALUE 1 1
0 1 E 0 0 0 1 1 4 0 0
9 0 0 1 1 0 0 B 1 1
7 1 1 1 1 0 0 9 0 0
2 1 1
9410-19.EPS
0
19/25
STV9410 5. CHARACTER CODE FORMAT
Each character is defined with a two bytes code; the first is at an even address, the second is at the following odd address. Some attributes are parallel, other keep the last explicit value. STV9410 uses 3 different types of codes. 5.1 ALPHANUMERIC CHARACTERS (256 patterns) The background color is not defined by the code; it takes the same value as the previous character or it has the value of the margin color at the beginning of each row. The character pattern lies in ROM if CHARACTER NUMBER is lower than 80h, (ALPHANUMERIC CHARACTER SET is shown in TABLE 3),else it is User Defined Character in RAM (DRCS).
ODD EVEN 0 IV CHARACTER NUMBER DW DH FL FC2 FC1 FC0 ODD EVEN EOL 1 1 1 1 EOL IF IB UL CC
BC2 BC1 BC0 HG FC2 FC1 FC0
CHARACTER : ROM or RAM character set code NUMBER IV : Inverted video if set. DW : Double character width if set, code must be repeated for the right part of the character. DH : Double character height if set, code must be repeated for the bottom part of the character. The first DH attribute encountered in a vertical column is always interpreted as a top part. FL : Flashing, inverted phase if IV is set. FC(2:0) : Foreground color (Green, Red, Blue).
: End Of Line 0 normal control code 1 space are displayed until the end of the row, allowing memory space saving IF,IB : Insert foreground, Insert background attribute. 0 fast blanking disable 1 fast blanking enable UL : Underlined 0 disable 1 enable CC : Conceal Character 0 disable 1 enable, character is diplayed as a space. BC(2:0) : Default background color of next character(s) HG : Hold Graphics 0 disable, the control character is displayed as a uniform space character with foreground color fixed by FC(2:0) 1 enable, the control character pattern takes the last mosaic value encountered in the row, if any, or is a space. FC(2:0) : G, R, B foreground value of the control character
At the beginning of each row, those attributes take default values : - EOL, UL, CC, HG = 0 - IF = 1 - IB = IMG (Margin insert attribute) - BC(2:0) = GMG, RMG, BMG (Margin color). Notice that following characters code is reserved for futur use.
ODD EVEN 1 1 1 X 1 X 1 X X X X X X X 1 X
5.2. GRAPHIC CHARACTERS (224 patterns) IV, DW, DH, UL take the value "0" CHARACTER NUMBER must be lower than E0h. The character pattern lies in ROM if CHARACTER NUMBER is lower than 80h, (STANDARD MOSAIC character set is shown in Table 4), else it is an User Defined Character in RAM (DRCS).
ODD EVEN 1 CHARACTER NUMBER BC2 BC1 BC0 FL FC2 FC1 FC0
6. CHARACTER GENERATORS
Each pixel is defined with one bit, 1 refers to foreground color, and 0 to background color.
PX7 PX6 PX5 PX4 PX3 PX2 PX1 PX0
CHARACTER NUMBER BC(2:0) FL FC(2:0)
: ROM or RAM character set code : Background color (Green, Red, Blue). : Flashing. : Foreground color (Green, Red, Blue).
5.3. CONTROL CHARACTERS (32 codes) These characters are displayed as foreground color spaces if HG bit is clear. They can change some attributes applying to themselves and to the following string.
PX7 is the leftmost pixel. Character slice address : Each character generator contains a succession of patterns arranged as a number of horizontal slices : - Slice addr = (Set addr) + Char Number x 10 + (slice number) - Char Number is the number of the character in the set; using DRCS in RAM, the calling code of the character is the number of the character in the set plus 80h. - Set addr is defined in ADDR register, in RAM for DRCS (see section 3.2), and is2000h for ALPHANUMERIC ROM, and 2800h for STANDARD MOSAIC ROM.
20/25
STV9410
Table 3 : Go AlphanumericCharacter Set 40 Character/Row STV9410
C6 C5 C4 C3 0 C2 0 C1 0 C0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
21/25
9410-20.EPS
STV9410
Table 4 : G1 Semigraphic Character Set
C6 C5 C4 C3 0 C2 0 C1 0 C0 0 SEPARATEDSEMI-GRAPHIC 0 0 0 0 0 0 1 1 0 1 0 1 MOSAIC SEMI-GRAPHIC 1 1 1 0 0 1 0 0 1 1 1 1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
22/25
9410-21.EPS
STV9410
TYPICAL APPLICATIONS CRT APPLICATION DIAGRAM
C S YNC
SYNC IN
VSYNC VDD
XTI
S CANNING
VREF
R, G, B
Y CRT
47pF
XTO
47pF
POR
S TV9410
I
VS S SDA
BUZZER
VSS A NCS SCK
MCU
LCD APPLICATION DIAGRAM
VDD VRE F
XTI
47pF
XTO
47pF
P OR
S TV9410
VEE LOAD FRAME D0 ... D3 CKD DF
320 x 2 50 LCD MATRIX
VSS SDA
BUZZER
VS SA NCS SCK
MCU
23/25
9410-23.EPS
CK0
9410-22.EPS
CK0
STV9410
PACKAGE MECHANICAL DATA 20 PINS - PLASTIC DIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.254 1.39
Millimeters Typ.
Max. 1.65
Min. 0.010 0.055
Inches Typ.
Max. 0.065
0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34
0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 0.053
DIP20.TBL
24/25
PM-DIP20.EPS
STV9410
PACKAGE MECHANICAL DATA 24 PINS - PLASTIC MICROPACKAGE
h x 45? A2 A1
A
0.10mm .004 Seating Plane
B
e
K L H
A1
C
D
24
13
SO24
Dimensions A A1 A2 B C D E e H h K L
Min. 2.35 0.1 0.33 0.23 15.20 7.40
Millimeters Typ.
Max. 2.65 0.30 2.55 0.51 0.32 15.60 7.60
Min. 0.093 0.004 0.013 0.009 0.598 0.291
Inches Typ.
Max. 0.104 0.012 0.100 0.020 0.013 0614 0.299 0.419 0.030 0.050
SO24.TBL
1.27 10.0 0.25 0.40 10.65 0.394 0.75 0.010 0o (Min.), 8o (Max.) 1.27 0.016
0.050
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
25/25
PM-SO24.EPS
1
12
E

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